A Generic Test Path and DUT Model for DataCom ATE

Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test

The combination of deep sub-micron technologies together with System on Chip complexity has brought the Device Under Test (DUT) Quiescent Supply Current (IDDQ ) into the Milliamps (mA) range. This IDDQ level, modulated by Electrical Parameters and Critical Dimensions Process spreads , makes almost impossible to detect the small current increase caused by the presence of a defect into the DUT. T...

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary andMVL is accomplished by digital to analo...

Hybrid Multisite Testing at Manufacturing

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for...

Cost Effective Test Methodology Using Pmu for Automated Test Equipment Systems

In this paper, test methodology using parametric measurement unit is proposed for Automated Test Equipment (ATE) systems using 600MHz Driver, Comparator, and Active load (DCL). ATE systems is a very important means to reduce the device test cost, and the systems should be able to test several modes to check the performance characteristics of the device. The proposed methodology provides four di...

DesignCon 2008 Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device Under Test Socket